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OpenSPARC with VHDL code available. SOLARIS IMAGES freely available ( Opensparc )




At the time of its release in December of 2005, a single chip, eight core, 32-thread, 1.2 GHz UltraSPARC T1 server performed similarly to a two-socket, four-core, eight-thread, 1.9 GHz IBM POWER5 server, performed similarly to a four socket, eight-core, sixteen-thread 3.0 GHz Intel Xeon "Paxville MP" server, and exceeded the performance of a four socket, four-core, four-thead 1.6 GHz Intel Itanium server. Arguably, this made the UltraSPARC T1 the world's most powerful general-purpose commercial server processor, when considering multithreaded commercial workloads.


The T2 is a derivative of the UltraSPARC series of microprocessors. The processor, manufactured in 65 nm, is available with eight CPU cores, and each core is able to handle eight threads concurrently. Thus the processor is capable of processing up to 64 concurrent threads. Other new features include:
Sun's insight of T2 SPARC processor and for the long awaited Rock Processor

Άλλο ένα δυνατό μηχανάκι από τη SUN. Μην τρέξετε όμως αμέσως να το αγοράσετε, είνα αποκλειστικά και μόνο για Server workloads

this made the UltraSPARC T1 the world's most powerful general-purpose commercial server processor, when considering multithreaded commercial workloads

Αν θέλετε brute force power πρέπει να δείτε το παρακάτω:



Αυτός είναι ο επεξεργαστής του PlayStation3.

The Cell Broadband Engine—or Cell as it is more commonly known—is a microprocessor designed to bridge the gap between conventional desktop processors (such as the well known Pentium and PowerPC families) and more specialised high-performance processors, such as nVIDIA and ATI graphics-processors (GPUs). The name indicates its intended use, namely as a component in current and future digital distribution systems; as such it may be utilised in high-definition displays and recording equipment, as well as computer entertainment systems for the HDTV era. Additionally the processor should be well suited to digital imaging systems (medical, scientific, etc.) as well as physical simulation (e.g. scientific and structural engineering modelling).

In a simple analysis the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE) (a two-way SMT Power 970 architecture compliant core), eight fully-functional co-processors called the Synergistic Processing Elements or SPEs and a specialised high-bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB.

To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding MPEG streams, generating or transforming three dimensional data, or undertaking Fourier analysis of data, the Cell processor simply marries the SPEs and the PPE via the EIB to give both access to main memory or other external data storage. The PPE which is capable of running a conventional operating system has control over the SPEs and can start, stop, interrupt and schedule processes running on the SPEs. To this end the PPE has additional instructions relating to control of the SPEs. Despite having Turing complete architectures the SPEs are not fully autonomous and require the PPE to initiate them before they can do any useful work. Most of the "horsepower" of the system comes from the synergistic processing elements.

The PPE and bus architecture includes various modes of operation giving different levels of memory protection, allowing areas of memory to be protected from access by specific processes running on the SPEs or PPE.

Both the PPE and SPE are RISC architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general purpose register set (GPR), a 64-bit floating point register set (FPR), and a 128-bit Altivec register set. The SPE contains 128-bit registers only. These can be used for scalar data types ranging from 8-bits to 128-bits in size or for SIMD computations on a variety of integer and floating point formats. System memory addresses for both the PPE and SPE are expressed as 64-bit values for a theoretic address range of 264 bytes. In practice, not all of these bits are implemented in hardware; the address space is extremely large nevertheless. Local store addresses internal to the SPU processor are expressed as a 32-bit word. In documentation relating to Cell a word is always taken to mean 32 bits, a doubleword means 64 bits, and a quadword means 128 bits.

Και ένα δείγμα μετρήσεων:



POWEEEEEEEEEEEEEER!!!

Σιγά το raw power. Καλό CPU αλλά... Να το χρησιμοποιησεις που?

Ακόμα και η IBM όταν πήγε να το βάλει σε server μηχανηματα αποφάσισε να το επανασχεδιάσει. Άστο λοιπόν το μηχανάκι αυτό άντε να μπεί σε κανά μπιμπλίκι PS3 HDTV κτλ...

Τα στατιστικά που παραθέτεις τυχαία ειναι

Να το χρησιμοποιησεις που?

Σε scientific calculations (FFT, πίνακες και άλλα τέτοια) δεν υπάρχει αντίστοιχο. Αυτά που φαίνονται στο πινακάκι είναι πραγματικές μετρήσεις και όπως βλέπεις καμία απολύτως σύγκριση.[/quote]

Ποιος θα μου πάρει ένα δώρο ?:Ρ
Θέλω να σας σκίσω στο SETI

Πϊστευω οτι σε 1 χρονο αν το ps3 έχει μπει για τα καλα στην αγορά, θα έχει αρκετά χαμηλη τιμή ώστε να το προτιμησεις από μια καλή κάρτα γραφικών (όπως το xbox360 τώρα), και μετα θα έχεις την επιλογή να βάλεις πανω ένα linuxaki και να κανεις το seti σε 1min το πακετο.

ps firegate ζητα το απο τον αγιο βασιλη

χε χε αργεί η πρωτοχρονιά ρε Under
Πάντως πιστεύω οτι το PS3 δεν έχει καμία τυχη.. Βλέπετε η τιμή του στα 660 ευρώ χωρίς ασύρματο χειριστήριο, χωρίς σκληρό δίσκο, και άλλα καλούδια που αναγκάστηκαν να κοπούν για να χαμηλώσει η τιμή του,συνεχίζει να είναι αρκετά ψηλή. Και αν αναλογιστεί κανείς την πολιτική να αγοράζει όλες σχεδόν τις κατασκεύαστριες εταιρίες παιχνιδιών τότε η sony θα τα βρει αρκετά δύσκολα..